SCSI Technologies

SCSI Technologies

SCSI is a system-level parallel channel or I/O bus designed for interconnecting peripheral devices that have intelligent controllers, thereby allowing control signals and data to flow to all peripherals.

Each SCSI drive consists of a disk drive, intelligent controller, and a SCSI port. The advantage that SCSI offers is that the bus supports a total of eight compatible peripherals or logical units. One of these logical units (LUNs) is an adapter card or host bus adapter (HBA) that is the interface between the seven other logical units and the system.

The HBA does not need to know how many cylinders, Heads, or sectors are available on each device. The local device intelligence is capable of managing these functions, including errors. The device may be Tape Drive,DAT Drive, CD-ROMs and other SCSI compliant devices.

This flexibility has caused compatibility problems in the past. Later versions of the standard, such as SCSI3 and Low Voltage Differential (LVD) SCSI, have more closely defined the standard and largely eliminated compatibility issues.

SCSI Basics

The SCSI standard, regardless of versions and implementation, features a number of unique characteristics. As part of the architecture,the bus offers distributed arbitration or bus-connection logic. The priority scheme awards interface control to the highest priority SCSI device that is contending for use of the bus.

SCSI IDs are usually set up on the drives by selecting a unique id number through an array of jumpers. SCSI devices are daisy chained together using a common 50-conductor A Cable or optional 68 conductor B Cable for Fast wide SCSI-2. All signals are common between all SCSI devices on the 50 or 68 pin cable.

Both ends of the SCSI chain are terminated and the termination may be internal to the devices that are on the ends of the cable. Communication on the SCSI bus is allowed between only two SCSI devices at any given time. When two SCSI devices communicate on the SCSI bus, one acts as an initiator and the other acts as a target. The initiator originates an operation and is responsible for target selection, and for providing commands and data. The target manages these commands and performs the operations. Information transfers on the data bus are asynchronous and conform to a REQ/ACK handshake.

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IDE Configuration-Few Things EXTRA

A Common IDE Drive


IDE translations

Standard CHS and the 528MB Barrier

The standard Cylinders-Heads-Sectors(CHS) scheme used on older PCs was limited to 1024 cylinders-16heads-and 64 sectors (denoted 1024/16/63) due to compatibility issues between the ATA/IDE interface, which links the hard drive to the BIOS and the int13th interface, which links the BIOS and DOS (or the O/S). Thus the maximum formatted drive capacity that could be used by the system was 528 MB, even if the actual drive capacity was greater.

The size limitation was due to the following differences between the interfaces, not the actual limitations of each interface:


Clearly each interface is individually capable of much more than 528Mb, but the lowest common denominator must be used in communication among the interfaces, the 528 MB is effective maximum capacity available to the system under the standard CHS scheme.

Extended CHS
Extended CHS (also reffered tp as large Disk Mode) attempted to break the 528MB barrier by translating the CHS parameters at the ATA/IDE interface. For example, if your drive has 1500 cylinders and 16 heads, a translating BIOS will make program thinks that the drive has 750 cylinders and 32 heads.

LBA (Logical Block Addressing)

With the Logical Block Addressing method, the standard addressing convention is replaced. The same registers are used to pass cylinder,head and sector information, but the information itself is completely redifined as a logical block address, such as an address found in SCSI.

LBA is a means of linearly addressing sector addresses, begining at sector 1 of head 0, Cylinder 0 as LBA 0 and proceeding on to the last physical sector on the drive, which for instance, on a standard 540 MB drive would be LBA1,065,456. This has always been the addressing mode used in SCSI.

LBA reduces CPU overhead because the operating system makes requests in LBA calls, which the BIOS normally must convert to CHS addressing before calling the drive. With LBA this conversion process is removed.

Master/Slave Relationships

A master /slave relationship exists when there are two hard drives connected to a single port. In this situation, one drive must be designated as the Master, or Primary drive and the other is Slave drive or secondary drive. This design is necessary because both the drives cannot work simultaneously.

Cable Select

Some computers use Cable Select technology for identifying IDE Hard Drive Device 0 (Master) and device 1 (Slave), depending on where they are connected on the Cable Select cable. The configuration jumpers on both HDD are set the same, Usually on the "CS" setting.

Cable Select hard drives and the IDE cables are Backward compatible with computers that do not support cable select. When a cable select HDD is used in a non cable select computer, the drive jumper must be reconfigured for Drive Select.

Drive Select

Drive select designates IDE HDD as master or slave based on jumper setting on HDD, not on position on the cable. When installing a slave drive with an existing single drive, the jumpers on the existing drive mayhave to be changed from "single" to "master". depending on the drive. For some drives, the single and master jumper settings are identical.

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PCI and ISA Technology

PCI Architecture

Basic Architecture:

The PCI bus is a local-bus design developed by Intel,Compaq,DEC,IBM and NCR in late 1991. The focus is oriented around electrical specifications at the expense of ease of integration. The PCI standard offers a number of features and advantages.
The fundamental design of PCI involves a buffered local bus, often reffered to as a mezzanine bus. The bus always uses some sort of PCI bridge, essentially removing the PCI bus from the host bus.
The most significant features and characteristics are:

• Provides switchless and jumperless support.
• Supports plug and play with no requirement to run a configuration utility in a PCI only system.
• Uses a multiplexed bus,which means that addresses and data move over the same set of wires.
• The processor independent design allows the bus to be supported under many processors.
• The bridging requirement protects against potential problems associated with high-speed host/local buses.
• Supports intelligent I/O devices and burst mode transfers of 132Mb/sec. The PCI bus may buffer read or write activity to allow the processor to continue with other tasks rather than waiting for the I/O operation to complete.
• Parity Checking is performed on all server PCI buses (control, address and data).
  

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Plug and Play Technology

History

In June 1993 the Plug and Play standard was created in conjunction with Microsoft, Intel, Compaq, HP, Toshiba and others. Its primary intent was to aid the user by automatically detecting and configuring newly inserted devices.

The Problem

The root of the problem is that when the PC was designed, no architecture was defined for installing, identifying, and configuring hardware devices or for integrating hardware and operating system software. One of great strengths of the PC is the wide variety of add-in devices for specialized functionality; yet the hardware and software configuration problem is compounded by the fact that the typical PC contains devices manufactured by a multitude vendors. The hardware, operating system, and applications cannot tell what the system contains, and the hardware cannot tell when conflicts exist between devices trying to share the same system resource. Before the advent of Plug and Play, users were forced to configure hardware through various means . Sometime a device had jumpers or a configuration utility. Still other portions of the system must be configured through the system BIOS.

The solution:Plug and Play

In practice, Plug and Play is both a design philosophy and set of PC architecture specifications. The ultimate goal pf Plug and Play is to enable changes to a PC configuration with no inventory by the user. A Plug and Play system has a number of characteristics . First any installation is simple , fail-safe operation. For devices the installation is automatic. Plug the device in, power on the system, and it works. With a Plug and Play system, the user can insert and remove certain devices (such as PCMCIA cards). The system determines the optimal configuration, and applications automatically adjust to take full advantage of the new configuration.

Plug and Play System design requirements

To deliver this Plug and Play functionality, the PC industry has developed an architecture that addresses several critical design requirements.

Easy Installation and Configuration
Plug and Play devices must be capable of identifying themselves and declaring their services and resource requirements. This information enables the operating system to determine and establish a working configuration for all devices on the system and to load the appropriate device drivers with minimal or no user intervention.
Seamless Dynamic Configuration
This capability is critical for mobile systems. The plug and Play architecture must allow hot docking and insertion of devices. When a device is inserted, the operating system must recognize the new device and its services or requirements.In the event that a driver is already present on the system, even latter step would not be required.
Installed base compatibility
The architecture must provide compatibility with the installed base of existing systems and peripherals and still meet the goal of easy installation and configuration of new devices.
Extensible Architecture
The architecture must support existing classes of devices and be extensible to new classes of devices that may arise in the future.
Open, Industry Standard
To make the solution comprehensive, the Plug and Play architecture is open and independent of specific operating systems and hardware implementations.
Reduced Complexity
To make the solution economically feasible for the industry , the architecture helps reduce hardware complexity and increase hardware flexibility.
Low Cost
Plug and Play is inexpensive to implement. In particular, it does not significantly increase the per-unit cost of PCs or devices.

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IDE Technology

IDE Basics

IDE/ATA

Integrated Drive Electronics (IDE) and AT Attachment (ATA) are the same: a disk drive configuration that integrates the controller onto the drive instead of on a card. With this configuration, interface costs are reduced, and firmware implementations are simplified.

EIDE

Contrary to popular belief, Enhanced IDE is not a standard. It is a marketing program consisting of a software part -- an Enhanced BIOS specification which breaks the 504 Mb barrier - and a hardware part that has been derived from the ATA2 (Hard Drives) and ATA p1 (Tapes, CD-Roms) standards. EIDE consists of four basic features.

• High Capacity Addressing of ATA Hard Drives - This feature is based on the AT Attachment (ATA) industry standard specification that defines how drives greater than 528 Mb are addressed by the system BIOS. Proper implementation requires that the drive, BIOS and operating system all support the ATA specification.
• Fast Data Transfer Rates for ATA Hard Drives - This feature is based on the ATA industry standard specifications for Programmed Input/Ooutput (PIO) mode 3 and Multiword Direct Memory Access (DMA) mode 1. These transfer modes support burst transfer rates of upto 11.1 MB/Sec and 13.3 MB/SEC. respectavely. The fast transfer capabilites take advantage of higher bandwidth of ATA local bus attachments, and are wasted if the drive is attached to a low bandwidth connection such as the ISA bus.
• Dual ATA Host Adapters - This feature uses a secondary host adapter address along with a secondary system interrupt (IRQ15) to address a second ATA host adapter, thus supporting upto four devices.
• Non-Hard Disk ATA peripherals - This feature is targeted at CDROM drives, tape drives and other peripherals that use the ATAPI (AT Attachment Packet Interface) specification command set. Previously, only hard drives could be connected to an IDE controller.

ATAPI

• The Western Digital authored AT attachment Packet Interface (ATAPI) specification is an EIDE and ATA specification that enables connectivity of non disk peripherals to an IDE controller. In other word, ATAPI is designed to allow devices such as CD-ROMs and tape drives to plug into an ordinary ATA (IDE) port. ATAPI is packet based interface whose command set is actually derived from SCSI. The principal advantage of ATAPI hardware is that it is inexpensive and works with existing host computer hardware and cabling.

IDE operation Modes and Speeds

PIO

Programmed I/O uses an interrupt driven method to transfer data. The following chain of events occurs:

1. A data request is made by the CPU.
2. The device (Disk Drive) retrieves the data.
3. The device then generates an interrupt to the processor.
4. The CPU responds to the interrupt and the data transfer begins.

This method is slow , but is simple and efficient in terms of hardware cost.
PIO modes are rated according to maximum data transfer speed. The modes range from 0 to 4, with a subsequent speed increase on each level. The modes and speeds are

• Mode 0 = 3.3 MB/s
• Mode 1 = 5.2 MB/s
• Mode 2 = 8.3 MB/s
• Mode 3 = 11.1 MB/s
• Mode 4 = 16.6 MB/s
  

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