PCI and ISA Technology

PCI Architecture

Basic Architecture:

The PCI bus is a local-bus design developed by Intel,Compaq,DEC,IBM and NCR in late 1991. The focus is oriented around electrical specifications at the expense of ease of integration. The PCI standard offers a number of features and advantages.
The fundamental design of PCI involves a buffered local bus, often reffered to as a mezzanine bus. The bus always uses some sort of PCI bridge, essentially removing the PCI bus from the host bus.
The most significant features and characteristics are:

• Provides switchless and jumperless support.
• Supports plug and play with no requirement to run a configuration utility in a PCI only system.
• Uses a multiplexed bus,which means that addresses and data move over the same set of wires.
• The processor independent design allows the bus to be supported under many processors.
• The bridging requirement protects against potential problems associated with high-speed host/local buses.
• Supports intelligent I/O devices and burst mode transfers of 132Mb/sec. The PCI bus may buffer read or write activity to allow the processor to continue with other tasks rather than waiting for the I/O operation to complete.
• Parity Checking is performed on all server PCI buses (control, address and data).